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| www.rfm.com email: info@rfm.com page 1 of 30 ?by rf monolithics, inc. TXC102 - 4/8/08 complies with directive 2002/95/ec (rohs) product overview TXC102 is a highly integrated single chip, multi-channel, low power, high data rate programmable rf transmitter ideal for the worldwide market and operates in the 433, 868 and 915 mhz frequency bands. the TXC102 is fcc & etsi certifiable and improves upon the txc101 with improved phase noise and is capable of higher out put power. all critical rf and baseband functions are completely integr ated in the chip, thus minimizing external component count and simplifyi ng design-ins. its small size with low power consumption makes it i deal for various short range radio applications. the TXC102 is a dual mode solution. in the micro controller mode, a generic 10mhz crystal and a low-cost microcontroller are the only requirements to create a complete transmitter link. in the eeprom mode, the TXC102 can function as a complete data transmitter with any spi compatible eeprom and does not need a micro controller. this makes it an ideal solution for a variety of si mple short range radio applications. key features ? modulation: ook/fsk ? frequency hopping spread spectrum capability ? operating frequency: 433/868/915 mhz ? low current consumption (tx current @ 0dbm ~ 13ma) ? wide operating supply voltage: 2.2 to 5.4v ? low standby current (0.2ua) ? ook data rate up to 512kbps ? fsk data rate up to 256kbps ? support for multiple channels: o [433 band]: 95 channels (100khz) o [868 band]: 190 channels (100khz) o [915 band]: 285 channels (100khz) ? generic 10mhz xtal reference ? processor or eeprom mode operation ? integrated pll, if & baseband circuitry ? integrated, programmable low battery voltage detector ? programmable push button control ? programmable output rf power ? programmable, positive/negative fsk deviation ? programmable clock output frequency ? standard spi interface ? external wake-up events ? ttl/cmos compatible i/o pins ? automatic antenna tuning circuit ? no manual adjustment needed for production ? very few external components requirement ? small size plastic package: 16-pin tssop ? standard 13 inch reel, 2000 pieces. 16-tssop package popular applications ? remote control applications ? remote control applications ? active rfid tags ? wireless pc peripherals ? automated meter reading ? home & industrial automation ? security systems ? remote keyless entry ? automobile immobilizers ? sports & performance monitoring ? wireless toys ? medical equipment ? low power two way telemetry systems ? wireless mesh sensors ? wireless modules TXC102 400-1000 mhz transmitter
www.rfm.com email: info@rfm.com page 2 of 30 ?by rf monolithics, inc. TXC102 - 4/8/08 table of contents table of contents ........................................................................................................................ 2 1.0 pin descriptions .................................................................................................................... 3 1.1 processor mode pin configuration ............................................................................... 3 1.2 eeprom mode pin configuration ................................................................................. 4 2.0 functional description ......................................................................................................... 5 2.1 TXC102 processor mode application ........................................................................... 5 rf transmitter matching................................................................................................. .. 5 antenna design considerations........................................................................................ 6 pcb layout considerations .............................................................................................. 6 2.2 eeprom mode application ............................................................................................ 8 3.0 TXC102 functional characteristics ................................................................................... 11 output amplifier .............................................................................................................. ...... 11 frequency control (pll) and frequency synthesizer .......................................................... 11 transmit register............................................................................................................. ..... 11 crystal oscillator ............................................................................................................ ....... 12 wake-up mode .................................................................................................................. ... 12 low battery detector.......................................................................................................... ... 12 key switch inputs............................................................................................................. ..... 12 spi interface ................................................................................................................. ........ 13 4.0 control and configuration registers ................................................................................ 14 table of control and configuration registers ....................................................................... 14 status register............................................................................................................... ....... 15 configuration register [por=8080h] ................................................................................... 16 transmit power configuration register [por=b0h] ............................................................. 18 transmit command register ................................................................................................ 19 frequency setting register [por=a7d0h]........................................................................... 20 data rate setup register [por=c800h].............................................................................. 21 button command register [por=ca00h]............................................................................ 22 sleep/clock command register [por=c400h] ................................................................... 23 wake-up timer period register [por=e000h] .................................................................... 24 battery detect threshold and bit synchronization register [por=c200h].......................... 25 power management register [por=c000h] ........................................................................ 26 5.0 maximum ratings ............................................................................................................... 27 recommended operating ratings........................................................................................ 27 6.0 dc electrical characteristics ............................................................................................. 27 7.0 ac electrical characteristics ............................................................................................. 28 8.0 transmitter measurement results .................................................................................... 30 9.0 etsi compliance ................................................................................................................. 31 reflow profile ............................................................................................................................ 33 10.0 package information ......................................................................................................... 34 www.rfm.com email: info@rfm.com page 3 of 30 ?by rf monolithics, inc. TXC102 - 4/8/08 1.0 pin description processor mode pin name description 1 sdi spi data in 2 sck spi data clock 3 ncs chip select input ? selects the chip for an spi data transaction. the pin must be pulled ?low? for a 16-bit read or write function. see figure 4 for timing specifications. 4 sw1 switch or push button input 1 with internal pull-up resistor 5 sw2 switch or push button input 2 with internal pull-up resistor 6 sw3 switch or push button input 3 with internal pull-up resistor 7 sw4 switch or push button input 4 with internal pull-up resistor 8 clkout optional host processor clock output 9 xtal/ref xtal - connects to a 10mhz series crystal or an external oscillator reference. the circuit contains an integrated load capacitor (see configuration register ) in order to minimize the external component count. the crystal is used as the reference for the pll, which generates the local oscillator frequency. the accuracy requirements for production tolerance, temperature drift and aging can be determined from the maximum allowable local oscillator frequen cy error. whenever a low frequ ency error is essential for the application, it is possible to ?pull? the crysta l to the accurate frequency by changing the load capacitor value. ext ref ? an external reference, such as an o scillator, may be connected as a reference source. connect through a .01uf capacitor. 10 gnd system ground 11 mode mode select ? connect to vdd for processor mode. 12 rf_p rf diff i/o 13 rf_n rf diff i/o 14 nirq interrupt request ? interrupt request output and status register data read output. 15 vdd supply voltage 16 mod modulation input ? serial data input for fsk or ook modulation 1.1 processor mode pin configuration www.rfm.com email: info@rfm.com page 4 of 30 ?by rf monolithics, inc. TXC102 - 4/8/08 eeprom mode pin name description 1 sdi spi data in 2 sck spi data clock 3 ncs chip select input - selects the chip for an spi data transaction. the pin must be pulled ?low? for a 16-bit read or write function. see figure 4 for timing specifications. 4 sw1 switch or push button input 1 with internal pull-up resistor 5 sw2 switch or push button input 2 with internal pull-up resistor 6 sw3 switch or push button input 3 with internal pull-up resistor 7 sw4 switch or push button input 4 with internal pull-up resistor 8 sdo spi data out 9 xtal/ref xtal - connects to a 10mhz series crystal or an external oscillator reference. the circuit contains an integrated load capacitor (see configuration register ) in order to minimize the external component count. the crystal is used as the reference for the pll, which generates the local oscillator frequency. the accuracy requirements for production tolerance, temperature drift and aging can be determined from the maximum allowable local oscillator frequen cy error. whenever a low frequ ency error is essential for the application, it is possible to ?pull? the crysta l to the accurate frequency by changing the load capacitor value. ext ref ? an external reference, such as an o scillator, may be connected as a reference source. connect through a .01uf capacitor. 10 gnd system ground 11 mode mode select ? connect to vss for eeprom mode. 12 rf_p rf diff i/o 13 rf_n rf diff i/o 14 nbd low battery detect ? when the battery voltage falls below the programmed level this output goes ?low?. the voltage level is programmable through the battery detect threshold register . 15 vdd supply voltage 16 mod not used . tie to vdd or vss 1.2 eeprom mode pi n configuration www.rfm.com email: info@rfm.com page 5 of 30 ?by rf monolithics, inc. TXC102 - 4/8/08 2.0 functional description the TXC102 is a low power, frequency agile, multi- channel ook/fsk transmitter for use in the 433, 868, and 916 mhz bands. all rf transmit functions are co mpletely integrated requiring only a single 10mhz crystal as a reference source. the TXC102 has two modes of operation: eeprom mode and processor mode. eeprom mode is fully compatible with any st andard spi interface eeprom. functions include: ? pll synthesizer ? power amp ? crystal oscillator ? sleep timer ? ook/fsk modulation ? 4 key/switch functions the TXC102 is ideal for frequency hopping spread s pectrum (fhss) applications requiring frequency agility to meet fcc and etsi requirements. use of a low-cost microcontroller or spi compatible eeprom is all that is needed to create a complete trans mitter. the TXC102 also incorporates different sleep modes to reduce overall current consumption an d extend transmitter battery life. it is ideal for applications operating from typical lithium coin cells. 2.1 TXC102 processor mode application circuit figure 1. typical processor mode 50 ohm load application circuit the TXC102 may be used with a typical low-cost microc ontroller. all internal functions are accessible through the spi interface. figure 1 shows a typical 50 ohm load connection for using a microcontroller to control the TXC102 functions. rf transmitter matching the rf pins are high impedance and differential. th e optimum differential load for the rf port at a given frequency band is shown in table 1. table 1. admittance [s] impedance [ohm] lantenna (nh) 433 mhz 1.3e-3 ? j6.3e-3 31 + j152 58 868 mhz 1.35e-3 - j1.2e-2 9 + j82 15.2 916 mhz 1.45e-3 - j1.3e-2 8.7 + j77 13.6 www.rfm.com email: info@rfm.com page 6 of 30 ?by rf monolithics, inc. TXC102 - 4/8/08 these values are what the rf port pins want to ?see? as an antenna load for maximum power transfer. antennas ideally suited for this would be a dipole, folded dipole, and loop. for all transmit antenna applications, a bias or ?choke? inductor must be in cluded since the rf outputs are open-collector type. the TXC102 may also drive a single ended 50 ohm load, such as a monopole antenna, using the matching circuit as shown in figure 1. use of a balun would provide an optimum power transfer, but the matching circuit of figure 1 has been optimized for us e with discrete components, reducing the cost associated with use of a balun. the matching component values for a 50 ohm load are given in table 2. table 2. ref des 433 868 916 c1 5.1pf 2.7pf 2.7pf c2 2.7pf 1.2pf 1.2pf l1 33nh 8.2nh 8.2nh l2 390nh 100nh 100nh l3 47nh 22nh 22nh antenna design considerations the TXC102 was designed to drive a differential output such as a dipole or a loop antenna. a loop antenna is recommended for applications where size is cr itical. the dipole is typically not an attractive option for compact designs based on its inherent size at resonance and distance needed away from a ground plane to be an efficient radiating antenna. a monopole is possible with addition of a balun or using the matching circuit in figure 1. pcb layout considerations pcb layout is very critical. for optimal transmit and receive performance, the trac e lengths at the rf pins must be kept as short as possible. using small, surface mount components, like 0402, will yield the best performance and also keep the rf port compact. it is recommended that all rf connections are made short and direct. a good rule of thumb to adhere to is to add 1nh of series inductance to the path for every 0.1? of trace length. the cr ystal oscillator is also affected by additional trace length as it adds parasitic capacitance to the overall load of the crystal. to minimize this effect the crystal must be placed as close as possible to the chip and all connections must be made short and direct. this will minimize the effects of ?frequency pulling? , that stray capa citance may introduce and allow the internal load capacitance of the chip to be more effective in properly loading the crystal oscillator circuit. when an external processor is used, the TXC102 pr ovides an on-chip clock. even though this is an integrated function, long runs of the clock signal may radiate and cause interference. this can degrade receiver performance as well as add harmonics or unwanted modulation to the transmitter. keep clock connections as short as possible and surround the clock trace with an adjacent ground plane pour where needed. this will help in reducing any radiation or cr osstalk due to long runs of the clock signal. good power supply bypassing is also essential. large decoupling capacitors should be placed at the point where power is applied to the pcb. smalle r value decoupling capacitors should then be placed at each power point of the chip as well as bias nodes for the rf port. poor bypassing lends itself to conducted interference which can cause noise and spurious signals to couple into the rf sections, thus significantly reducing performance. www.rfm.com email: info@rfm.com page 7 of 30 ?by rf monolithics, inc. TXC102 - 4/8/08 top bottom top assembly www.rfm.com email: info@rfm.com page 8 of 30 ?by rf monolithics, inc. TXC102 - 4/8/08 2.2 eeprom mode figure 2. typical eeprom mode 50 ohm load application circuit the TXC102 can operate from a singl e, spi compatible eeprom by simp ly reading the sequential codes stored in memory. no external microcontroller is required. the codes are read out and processed as command and data. in this special mode, four pins are configured as inputs with an internal pull-up resistor. all that is needed are external key swit ches connected to gnd to activate that key?s code routine. when the key is pressed, the chip autom atically begins executing code from a designated point within the eeprom. when not in use, the last command of the code execution should be a sleep command so as to power down the device for maximum battery life. when the device is put into sleep one of the following seven (7) events can cause the device to wake up: ? power-on reset ? low pulse on key 1 ? low pulse on key 2 ? low pulse on key 3 ? low pulse on key 4 ? low supply voltage output warning ? wake-up timer timeout for each wake-up event there is an internal address assigned as th e starting point in eeprom memory to begin executing code. these are defined in table 3 as follows: table 3. wake-up event eeprom address entry power up 0000h low pulse on sw1 0080h low pulse on sw2 0100h low pulse on sw3 0180h low pulse on sw4 0200h lbd warning 0280h wake-up timer timeout 0300h www.rfm.com email: info@rfm.com page 9 of 30 ?by rf monolithics, inc. TXC102 - 4/8/08 another feature allows the use of two keys being pr essed at the same time. for this, bit7 in the button command register controls whether sw4 is used as a single key press or sw1 and sw2 are used as simultaneous key presses. by setting bit7 of the button command register, the eeprom address entry point of sw4 is used for si multaneous presses of sw1 and sw2. clearing bit7 sets the eeprom to use sw4 as a single key press. it is also po ssible to detect multiple key presses and execute sequential routines. when multiple keys are pressed, all routines associated with the keys are executed in the same sequence of which the keys were pressed. when a key is pressed, the chip looks to see if t here is a debounce time to recognize before sampling the pin again. at this time the oscillator is tur ned on, independent of the state of bit 5 of the power management register , because it uses the crystal oscillator si gnal as a timing reference. after the debounce time has expired, it begi ns execution of the code from t he eeprom address entry point. all sources used to transmit are internal when using eeprom mode. all external pin functions, such as external fsk modulation, are disabled and the inte rnal functions are used. during sleep mode, all internal configurations are maintained as long as powe r is not interrupted. if there is a supply interruption the chip reboots from t he power-up eeprom address entry point and a ll configurations are re-written. example eeprom hex code contents: power-on reset: 00000000 c0 c4 ca 1e c8 23 c4 64 00 00 00 00 00 00 00 00 00000010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00000020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00000030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00000040 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00000050 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00000060 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00000070 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 the example above configures the initial settings of t he registers at power-up. other parameters may be changed as needed when the chip recognizes a key press. the code ends in a sleep command c400h where 00h is the number of clocks to output bef ore disabling the clock output pin. see sleep/clock command register . address command data related register description 00?01 c0 c4 power management crystal? synthesizer ? power amplifier auto on/off mode enable 02?03 ca 1e button command continuous execution for all keys 04?05 c8 23 data rate dr=10m/29/(35+1)~9600 bps 06-07 c4 64 sleep power down after 64h (100) clocks example code for key press 3: in the above example, some command s are one nibble long. for purposes of writing to the eeprom the data must be arranged in bytes. the chip automatic ally distinguishes between command and data. on 00000180 88 72 a6 10 c6 60 aa aa aa aa aa aa aa aa aa aa 00000190 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa 000001a0 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa 000001b0 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa 000001c0 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa 000001d0 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa 000001e0 aa aa aa aa aa aa c4 00 00 00 00 00 00 00 00 00 000001f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 www.rfm.com email: info@rfm.com page 10 of 30 ?by rf monolithics, inc. TXC102 - 4/8/08 power-up, the keys are configured as a single execution. hence, after this routine is executed, the chip returns to sleep and wakes up on another key press. if the keys were configured as a continuous execution, at the end of the sleep command, the chip restarts at address 0180h and re-executes the routine until the key is released. 3.0 TXC102 functional characteristics figure 3. functional block diagram output power amplifier the power amplifier is an open-collector, different ial output with programmable output power which can directly drive a loop or dipole antenna, and with proper matching may also drive a monopole antenna. incorporated in the power amplifier is an automatic antenna tuning circuit to avoid manual tuning during production and to offset ?hand effects?. registers common to the power amplifier are: ? power management register ? transmit power configuration register phase lock loop (pll) the pll synthesizer is the heart of the operating fr equency. an integrated lc oscillator gives the TXC102 superior performance over it txc101 counterpart with lower phase noise. it is programmable and completely integrated, providing all functions r equired to generate the carriers and tunability for each band. the pll requires only a single 10mhz crystal reference source. rf stability is controlled by choosing a crystal with the particular specif ications to satisfy the application. address command data related register remarks 180?181 8 872 configuration control 433mhz band, fsk dev=90khz, crystal cl=12pf 182?183 a 610 frequency fc=(43+1552/4000)*10mhz [433.92mhz] 184?185 c6 60 data transmit transmit the next 96 bytes 186?1e5 96xaah data 1e6?1e7 c4 00 sleep power down immediately (no clocks) www.rfm.com email: info@rfm.com page 11 of 30 ?by rf monolithics, inc. TXC102 - 4/8/08 the pll is able to perform manual and automatic calib ration to compensate for changes in temperature or operating voltage. when changing band frequencies, re-calibration must be performed. this can be done by disabling the synthesizer and re-enabling again through the power management register . registers common to the pll are: ? power management register ? configuration register ? frequency setting register ? transmit configuration register transmit register the transmit register is configured as two 8-bit shift registers connected in series to form a single 16-bit shift register. this register is a master when in eeprom mode. t he TXC102 generates the chip select and clock to read the eeprom contents into the register. for microcontroller mode, this register is not availabl e. data may be applied in two ways: directly to the fsk mod pin (16) after enabling the oscillator, synthesiz er, and power amplifier, or directly to the sdi pin following the clock timing on page 19 of the transmit command register . the TXC102 has a bit synchronization circuit that issues an interrupt to the microcontroller when the next bit should be applied to the mod pin. this feature is enabled through the battery detect threshold and bit synchronization register. see the individual register for timing details. the data rate must be set through the data rate setup register in order to use this feature. crystal oscillator the TXC102 incorporates an internal crystal oscillator ci rcuit that provides a 10mhz reference, as well as internal load capacitors. this significantly reduces the component count required. the internal load capacitance is programmable from 8.5pf to 16pf in 0. 5pf steps. this has t he advantage of accepting a wide range of crystals from many different manufactu rers having different load capacitance requirements. since the crystal is the pll reference for the carrier, being able to vary the load capacitance also helps with fine tuning the final carrier frequency. an external clock signal is also provided that may be used to run an external processor. this also has the advantage of reducing component c ount by eliminating an additional cr ystal for the host processor. the clock frequency is also programmable from eigh t pre-defined frequencies, each a pre-scaled value of the 10mhz crystal reference. these values are programmable through the battery detect threshold and clock output register. the internal clock oscillator may be dis abled, thus also disabling the output clock signal to the host processor. when the oscillator is disabled, the chip provides an additional 196 clock cycles before releasing the output, which may be used by the host processor to setup any functions before going to sleep. sleep mode the TXC102 draws very little current when in sleep mode (200na typical). see the power management register and sleep/clock command register definitions on how to program the TXC102 into full sleep mode. wake-up mode the TXC102 has an internal wake-up timer that has very low current consumpt ion (1.5ua typical) and may be programmed from 1msec to several days. a calibration is performed to the crystal at startup and every 30 sec thereafter, even if in sl eep mode. if the oscillator circuit is disabled the calibration circuit will turn it on briefly to perform a calibration to ma intain accurate timing and return to sleep. the TXC102 also incorporates other power saving modes aside from the wake-up timer. return to active mode may be initiated from several external events: ? logic ?0? applied to nint pin (16) ? low supply voltage detect ? fifo fill ? spi request www.rfm.com email: info@rfm.com page 12 of 30 ?by rf monolithics, inc. TXC102 - 4/8/08 if any of these wake-up events occu r, including the wake-up timer, the TXC102 generates an external interrupt which may be used as a wake-up signal to a host processor. the source of the interrupt may be read out from the status register over the spi bus. to re-enter wake-up mode the wkupen bit (1) of the power management register must be cleared then set. low battery detect the integrated low battery detector monitors t he voltage supply against a preprogrammed value and generates an interrupt when the supply voltage falls below the programmed value. the detector circuit has 50mv of hysteresis built in. key switch inputs in microcontroller mode, the TXC102 generates an inte rrupt on the nirq pin when a key is pressed. the source of the interrupt may be determined by reading the status register . in eeprom mode, each switch has an internal address assigned to it. it us es this address as the entry point to the eeprom and executes commands after that address until it sees a sleep command (c400h). the chip has internal weak pull-up resistors so there is no need for additional components. these weak pull-ups may be disabled through the button command register. for each mode the chip repeats this function while the key is pressed if configured by the button command register . in the microcontroller mode, the chip continuously generate s interrupts until the key is released. in the eeprom mode, the chip continuously enters the eeprom at the assigned address and executes the command s following the entry point as long as the key is active, if enabled through the button command register . there are seven defined entry points for the eeprom mode. the chip also has an integrated, progra mmable de-bounce circuit for each key. see button command register for a detailed explanation. spi interface the TXC102 is equipped with a standard spi bus that is compatible to almost all spi devices. all functions and status of the chip are accessible thro ugh the spi bus. typical spi devices are configured for byte write operations. the TXC102 uses word writ es and hence the ncs (pin 3) should be pulled low for 16 bits. www.rfm.com email: info@rfm.com page 13 of 30 ?by rf monolithics, inc. TXC102 - 4/8/08 table 4. figure 4. timing diagram www.rfm.com email: info@rfm.com page 14 of 30 ?by rf monolithics, inc. TXC102 - 4/8/08 4.0 control and conf iguration registers bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit por value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 status x x x x x x x x 1 1 0 0 1 1 0 0 - - config 1 0 0 band1 band0 clk2 clk1 clk0 cap3 cap2 cap1 cap0 modp dev2 dev1 dev0 8080h tx power config x x x x x x x x 1 0 1 1 ooken pwr2 pwr1 pwr0 xxb0h tx command reg 1 1 0 0 0 1 1 0 b7 b6 b5 b4 b3 b2 b1 b0 - - freq set 1 0 1 0 freq11 freq10 freq9 freq8 freq7 freq6 freq5 freq4 freq3 freq2 freq1 freq0 a7d0h data rate set 1 1 0 0 1 0 0 0 bitr7 bitr6 bitr5 bitr4 bitr3 bitr2 bitr1 bitr0 c800h button cmd 1 1 0 0 1 0 1 0 2kpen db1 db0 sw4 sw3 sw2 sw1 pupdis ca00h sleep/clk cmd 1 1 0 0 0 1 0 0 slp7 slp6 slp5 slp4 slp3 slp2 slp1 slp0 c400h wake-up period 1 1 1 r4 r3 r2 r1 r0 mul7 mul6 mul5 mul4 mul3 mul2 mul1 mul0 e000h batt detect and bit synch 1 1 0 0 0 0 1 0 wcal 0 bsync lbd4 lbd3 lbd2 lbd1 lbd0 c200h power management 1 1 0 0 0 0 0 0 tx1 tx0 oscen synen paen lbden wkupen clken c000h x-not used table 5. control and configuration registers table status register ( read only ) bit bit bit bit bit bit bit bit 7 6 5 4 3 2 1 0 1 1 0 0 1 1 0 0 the status register provides feedback for: ? por ? interrupt request state ? low battery ? push button event the status register requires only the command code to be sent. st atus bits can be read out through the nirq pin (14). clock pulses are continually sent and data is read out. when this co mmand is issued it clears the last interrupt and starts processi ng the next pending interrupt. see figure 5 for read sequence. figure 5. status register read through nirq pin (14) bit [7..0]: command code: these bits are the command code that is sent serially to the processor that identifies the bits to be written to the status register. ncs www.rfm.com email: info@rfm.com page 15 of 30 ?by rf monolithics, inc. TXC102 - 4/8/08 configuration register [por=8080h] bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 band1 band0 clk2 clk1 clk0 cap3 cap2 cap1 cap0 modp dev2 dev1 dev0 the configuration register sets up the following: ? frequency band in use ? crystal load capacitance ? tx modulation polarity ? tx modulation bandwidth bit [15..13] ? command code: these bits are the command code that is sent serially to the processo r that identifies the bits to be written to the configuration register. bit [12..11] ? band select: these bits set the frequency band to be used. there are four (4) bands that are supported. see table 6 below for band configuration. table 6. bit [10..8] ? clock output frequency: these bits set the output frequency of the on-board clock that may be used to run an external host processor. see table 7 below. table 7. bit [7..4] ? load capacitance select: these bits set the load capacitance for the cryst al reference. the internal load capacitance can be varied from 8.5pf to 16pf in 0.5pf steps to acco mmodate a wide range of crystal vendors and also to adjust the reference frequency and compensate for stray capacitance that may be introduced due to pcb layout. see table 8 below for load capacitance configuration. table 8. bit [3] - modulation polarity: when clear, a logic ?0? is defined as the lower channel frequency and a logic ?1? as the higher channel frequency (positive deviation). when set, a logic ?0? is defined as the higher chann el frequency and a logic ?1? as the lower channel frequency (negative deviation). frequency band band1 band0 433 0 1 868 1 0 916 1 1 output clock frequency (mhz) clk2 clk1 clk0 1 0 0 0 1.25 0 0 1 1.66 0 1 0 2 0 1 1 2.5 1 0 0 3.33 1 0 1 5 1 1 0 10 1 1 1 cap3 cap2 cap1 cap0 crystal load capacitance 0 0 0 0 8.5 0 0 0 1 9 0 0 1 0 9.5 0 0 1 1 10 ?? ?? 1 1 1 0 15.5 1 1 1 1 16 www.rfm.com email: info@rfm.com page 16 of 30 ?by rf monolithics, inc. TXC102 - 4/8/08 configuration register ? continued bit [2..0] - modulation bandwidth: these bits set the fsk frequency deviation fo r transmitting a logic ?1? and logic ?0?. the deviation is programmable from 30khz to 210khz in 30k hz steps. see table 9 bel ow for deviation settings. table 9. modulation bandwidth hex dev2 dev1 dev0 30 khz 00 0 0 0 60 khz 01 0 0 1 90 khz 02 0 1 0 120 khz 03 0 1 1 150 khz 04 1 0 0 180 khz 05 1 0 1 210 khz 06 1 1 0 not used 07 1 1 1 transmit power configuration register [por=b0h] bit bit bit bit bit bit bit bit 7 6 5 4 3 2 1 0 1 0 1 1 ooken pwr2 pwr1 pwr0 the power configuration register confi gures the output transmit power desired. bit [7..4] - command code: these bits are the command code that is sent serially to the processor that identifies the bits to be written to the transmit power configuration register. bit [3] ? ooken: this bit enables ook mode for the power amplifier. in th is mode, data is applied to the mod pin (16). when a logic ?1? is applied, the power amplifier is on. when a logic ?0? is applied, the power amplifier is off. bit [2..0] ? output transmit power: these bits set the transmit output power. th e output power is programmable from max to -21db in -3db steps. see table 10 below for output power settings. table 10. output power (relative) pwr2 pwr1 pwr0 max 0 0 0 -3db 0 0 1 -6db 0 1 0 -9db 0 1 1 -12db 1 0 0 -15db 1 0 1 -18db 1 1 0 -21db 1 1 1 transmit command register [por=c600h] (eeprom mode) bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 0 1 1 0 b7 b6 b5 b4 b3 b2 b1 b0 (processor mode) bit bit bit bit bit bit bit bit 7 6 5 4 3 2 1 0 1 1 0 0 0 1 1 0 www.rfm.com email: info@rfm.com page 17 of 30 ?by rf monolithics, inc. TXC102 - 4/8/08 the transmit command register in eeprom mode holds the count of the number of data bytes to follow. in processor mode, only the command code is sent and the data is applied to the sdi pin without a clock. if clock pulses are sent, the data will be interpreted as commands. in this mode the sdi pin acts like the mod input pin (16). see figure 6. t sx is the oscillator startup time t sp is the synthesizer start-up and lock time figure 6. data transmit through sdi pin the mod pin(16) may also be used to manually send modulated data. the oscillator and synthesizer must manually be enabled through the power management register. startup and settle time must be allowed before applying a modulating signal to the mod pin(16). bit [15..8] - command code: these bits are the command code that is sent serially to the processor that identifies the bits to be written to the transmit command register. bit [7..0] ? byte count (eeprom mode only) : these bits are the 8-bit value of the number of data bytes to be transmitted. before issuing this command the power amplifier must be enabled either by setting the respective power management register bits paen bit (3) or tx0 bit (6). bit [7..0] - command code (processor mode only) : these bits are the command code that is sent serially to the processor that identifies the bits to be written to the transmit command register. note: when manually controlling the oscillator and synthesizer turn-on, valid data can only be transmitted when the oscillator has had time to start-up and the synthesizer has had time to lock. data may also be sent through the fsk pin (16). when the transmit command is issued the osc and synthesizer are automatically enabled. if the osc and synthesizer are not running, there must be a delay before sending out the first bit in o rder to allow the osc to stabilize and the synthesizer to lock. see figure 7 timing below. figure 7. data transmit through fsk pin ncs sck sdi www.rfm.com email: info@rfm.com page 18 of 30 ?by rf monolithics, inc. TXC102 - 4/8/08 frequency setting register [por=a7d0h] bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 0 freq11 freq10 freq9 freq8 freq7 freq6 freq5 freq4 freq3 freq2 freq1 freq0 the frequency setting register sets the exact frequency within t he selected band for transmit or receive. each band has a rang e of frequencies available for channelization or frequency hopping. the selectable frequencies for each band are: frequency band min (mhz) ma x (mhz) tuning resolution 400 mhz 430.24 439.75 2.5 khz 800 mhz 860.48 879.51 5.0 khz 900 mhz 900.72 929.27 7.5 khz bit descriptions are as follows: bit [15..12] ? command code: these bits are the command code that is sent serially to the processo r that identifies the bits to be written to the frequency setting register. bit [11..0] ? frequency setting: these bits set the center frequency to be used duri ng transmit or receive. the value of bits[11..0] must be in the decimal range of 96 to 3903. any value outsi de of this range will cause the previous value to be kept and no frequency change will occur. to calculate the center frequency f c , use table 11 below and the following equation: f c = 10 * b1 * (b0 + f val /4000) mhz where f val = decimal value of freq[11..0] = 96 www.rfm.com email: info@rfm.com page 20 of 30 ?by rf monolithics, inc. TXC102 - 4/8/08 sleep/clock command register [por=c400h] bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 0 1 0 0 slp7 slp6 slp5 slp4 slp3 slp2 slp1 slp0 the sleep command register defines the byte command and the number of clock cycles to generate after a sleep instruction to put the chip into sleep mode. when the chip sees this command issued, it immediately disables the power amplifier, turns off the synthesizer, and turns off the oscillator after slp[7..0] clock cycles. bit [15..8] ? command code: these bits are the command code that is sent serially to the processor that identifies the bits to be written to the sleep command register. bit [7..0] ? sleep command value: these bits define the number of clock cycles to generate before disabling the oscillator and before the chip goes into sleep mode. this allows time fo r an external processor to perform any memory or pre-sleep functions before the clock is stopped and the device enters sleep mode. wake-up timer period register [por=e000h] bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 r4 r3 r2 r1 r0 mul7 mul6 mul5 mul4 mul3 mul2 mul1 mul0 the wake-up timer period register sets the wake-up interval for the TXC102. after setting the wake-up interval, the wkupen (bi t 1 of power management register ) should be cleared and set at the end of every wake- up cycle. to calculate the wake-up interval desired, use the following: t wake = mul[7..0] * 2 r[4..0] where mul[7..0] = decimal value 0 to 255 and r[4..0] = decimal value 0 to 31. bit [15..13] ? command code: these bits are the command code that is sent serially to the processo r that identifies the bits to be written to the wake-up timer period register. bit [12..8] ? exponential: these bits define the exponential va lue as used in the above equation. the value used must be the decimal equivalent between 0 and 31. bit [7..0] ? multiplier: these bits define the multiplier value as used in t he above equation. the value used must be the decimal equivalent between 0 and 255. battery detect threshold and bit synchronization register [por=c200h] bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 0 0 1 0 wcal 0 bsync lbd4 lbd3 lbd2 lbd1 lbd0 the battery detect threshold and clock output register configures the following: ? low battery detect threshold the low battery threshold is programmable from 2.2v to 5.3v using the following equation: vt = (lbd[4..0] / 10) + 2.2 (v) where lbd[4..0] is the decimal value 0 to 31. bit [15..8] - command code: these bits are the command code that is sent serially to the processor that identifies the bits to be written to the battery detect threshold register. bit [7] ? wcal: when set, this bit disables the wake-up timer calibration. when enabled, calibration is performed every 30 secs. www.rfm.com email: info@rfm.com page 21 of 30 ?by rf monolithics, inc. TXC102 - 4/8/08 bit [6] ? not used. write a logic ?0?. bit [5] ? bsync: when set, this bit enables the transmitter bit sync hronization according to the data rate set in the data rate setup register. the TXC102 issues an interrupt when the next bit should be applied to the mod pin. figure 7 shows the timing for bit synchronization. figure 7. bit synchronization timing diagram bit [4..0] ? low battery detect value: these bits set the decimal value as used in the equation above to calculate the battery detect threshold voltage value. when the battery level falls 50mv be low this value, the lbd bit (5) in the status register is set indicating that the battery level is below the programmed th reshold. this is useful in monitoring discharge sensitive batteries such as lithium cells. the low battery detect can be enabled by setting the lbden bit (2) of the power management register and disabled by clearing the bit. power management register [por=c000h] bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 0 0 0 0 tx1 tx0 oscen synen paen lbden wkupen clken the power management register enables/disables the following: ? transmit chain ? pll ? power amplifier ? synthesizer ? crystal oscillator ? low battery detect circuit ? wake-up timer ? clock output bit [15..8] ? command code: these bits are the command code that is sent serially to the processor that identifies the bits to be written to the power management register. bit [7..6] ? transmit chain automatic enable: these bits enable the entire transmit c hain when set. when tx1 is set, the oscillator and synthesizer turn-on ar e controlled by the chip. when the data transmit command is issued, the oscillator is enabled. as soon as a stable frequency is reached the synthesizer is enabled. when tx0 is set, this turns on the power amplifier after the pll has successfully achieved lock. table 14 function tx1 tx0 manual 0 0 pa on after synth locked 0 1 osc and synth on when transmit cmd issued 1 0 osc and synth on after transmit cmd, then pa on after synth locked 1 1 spi cmds nirq mod or sdi data www.rfm.com email: info@rfm.com page 22 of 30 ?by rf monolithics, inc. TXC102 - 4/8/08 bit [5] ? crystal oscillator enable: this bit enables the oscillator circuit when set. the oscillator provides the reference signal for the synthesizer when setting the transmit frequency of use. bit [4] ? synthesizer enable: this bit enables the synthesizer when set. the synt hesizer contains the pll, oscillator, and vco for controlling the channel frequency. this must be enabled when the transmitter is enabled. the oscillator also must be enabled to provide the reference frequency for the pll. on pow er-up the synthesizer performs a calibration automatically. if there are significant changes in voltage or temperature, reca libration can be performed by simply disabling the synthesizer and re-enabling it. note: for correct operation of the frequency synthesizer, the frequency and band of operation need to be programmed before the synthesizer is started. directly after activation of the synt hesizer, the rf vco is calibrated to ensure proper operation in th e programmed frequency band. it is suggested that recalibration routines be added to compensate for significant changes in temperature and supply voltages. bit [3] ? power amplifier enable: this bit enables the power amplifier when set. the power amplifier may be manually enabled from other functions. bit [2] ? low battery detector: this bit enables the battery voltage detect circ uit when set. the battery detector can be programmed to 32 different threshold levels. see battery detect threshold and clock output register section for programming. bit [1] ? wake-up timer enable: this bit enables the wake-up timer when set. see wake-up timer period register section for programming the wake-up timer interval value. bit [0] ? clock output disable: this bit disables the oscillator clock output when set. on chip reset or power up, clock output is on so that a processor may begin execution of any spec ial setup sequences as required by the designer. see battery detect threshold and clock output register section for programming details. sleep mode the device enters sleep mode by writing a 0x c001 which disables all functions and tu rns off the clock output. if the clock out put is not disabled by writing a ?1? to bit 0, the oscillator ci rcuit will continue to run a nd draw additional current. 5.0 maximum ratings absolute maximum ratings symbol parameter notes min max units vdd positive supply voltage -0.5 6 v v in voltage on any pin (except rf_p and rf_n) -0.5 vdd+0.5 v voc voltage on open collector outputs (rf1, rf2) 1 -0.5 6 v i in input current into any pin except vdd and vss -25 25 ma esd electrostatic discharge with human body model 1000 v t stg storage temperature -55 125 c t lead lead temperature (soldering, max 10 s) 260 c note 1: at maximum, vdd+1.5 v cannot be higher than 7 v. recommended operation ratings symbol parameter notes min max units vdd positive supply voltage 2.2 5.4 v vdc rf dc voltage on open collector outputs (rf1, rf2) 1,2 vdd-1 vdd+1 v t op ambient operating temperature -40 85 c note 1: at minimum, vdd - 1.5 v cannot be lower than 1.2 v. note 2: at maximum, vdd+1.5 v cannot be higher than 5.5 v. www.rfm.com email: info@rfm.com page 23 of 30 ?by rf monolithics, inc. TXC102 - 4/8/08 6.0 dc electrical characteristics (min/max values are valid over the whole recommended operating range vdd = 2.2-5.4v. typical conditions: top = 27c; vdd = 3.0 v) digital i/o sym notes limit values unit test conditions parameter min typ max 13 14 433mhz band 14 15 868mhz band supply current (tx mode, pout = 0dbm, into 50 ohm load) idd tx0 15 16 ma 916mhz band 21 23 433mhz band 22 24 868mhz band supply current (tx mode, pout = pmax, differential or 50 ohm load) idd tx 23 25 ma 916mhz band sleep current i s 0.2 a all blocks disabled idle current i idle 1.5 ma oscillator and baseband enabled low battery voltage detector current consumption i vd 0.5 a wake-up timer current consumption i wut 1.5 a low battery detect threshold vlb 2.2 5.3 v programmable in 0.1 v steps low battery detection accuracy 75 mv digital input low level vil 0.3*vdd v digital input high level vih 0.7*vdd v digital input current low iil -1 1 a vil = 0 v digital input current high iih -1 1 a vih = vdd, vdd = 5.4 v digital output low level vol 0.4 v iol = 2 ma digital output high level voh vdd-0.4 v ioh = -2 ma digital input capacitance 2 pf digital output rise/fall time 10 ns load = 15 pf www.rfm.com email: info@rfm.com page 24 of 30 ?by rf monolithics, inc. TXC102 - 4/8/08 7.0 ac electrical characteristics (min/max values are valid over the whole recommended operating range vdd = 2.2-5.4v. typical conditions: top = 27c; vdd = 3.0 v) transmitter sym notes limit values unit test conditions parameter min typ max open collector output dc current 0.5 6 ma programmable +8 433 mhz band +6 868 mhz band output power (differential load) p dl +6 dbm 916 mhz band 2 +6.5 433 mhz band 2 +5.7 868 mhz band output power (50 ohm load) p o +5 dbm 916 mhz band -65 433mhz band -70 868mhz band reference spur -75 dbm 916mhz band 3 -41 433mhz band 3 -40 868mhz band 2nd harmonics -38 dbm 916mhz band 3 -48 433mhz band 3 -50 868mhz band 3rd harmonics -50 dbm 916mhz band 1.5 2.3 3.1 433mhz band 868mhz band antenna tuning capacitance 1.6 2.2 2.8 pf 916mhz band 433mhz band 868mhz band output capacitance quality factor 16 18 22 916mhz band -85 100 khz from carrier phase noise 1 -105 dbc/hz 1 mhz from carrier fsk bit rate 1 256 kbps fsk = 210khz ook bit rate 512 kbps fsk frequency deviation 15 210 khz programmable in 30 khz steps www.rfm.com email: info@rfm.com page 25 of 30 ?by rf monolithics, inc. TXC102 - 4/8/08 timing sym notes limit values unit test conditions parameter min typ max internal por timeout 100 ms vdd at 90% of final value wake-up timer period 0.95 1.05 ms calibrated every 30 seconds wake-up time 1 2e+9 ms pll characteristics sym notes limit values unit test conditions parameter min typ max pll reference freq 8 10 12 mhz pll lock time 10 us within 1khz settle, 10mhz step pll startup time 250 us crystal running crystal load capacitance cl 8.5 16 pf programmable in 0.5 pf steps, tolerance +/- 10% xtal oscillator startup time 5 ms crystal esr < 100 430.24 439.75 433mhz band (2.5khz steps) 860.48 879.51 868mhz band (5.0khz steps) tuning range (w/ 10mhz ref xtal) 900.72 929.27 mhz 916mhz band (7.5khz steps) notes: 1- the phase noise and max data rate is dependent on the pll configuration. 2- output power increases 1 db without ad ditional pi filter for etsi compliance. 3- with added 3-pole pi filter as defined in section 9.0. pll command data rate (kbps) phase noise at 1mhz offset (dbc/hz) description d240h 19.2 -112 25% current d2c0h 28 -110 33% current d200h 64 -107 50% current (por default) d280h 115 -102 100% current www.rfm.com email: info@rfm.com page 26 of 30 ?by rf monolithics, inc. TXC102 - 4/8/08 8.0 transmitter measurement results current vs voltage at max output power 17.0 18.0 19.0 20.0 21.0 22.0 23.0 24.0 25.0 26.0 27.0 2.2v 3.0v 5.4v voltage (v) current (dbm) 433mhz 868mhz 915mhz max output power vs voltage 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 2.2v 3.0v 5.4v voltage (v) output power (dbm) 433mhz 868mhz 915mhz www.rfm.com email: info@rfm.com page 27 of 30 ?by rf monolithics, inc. TXC102 - 4/8/08 9.0 etsi compliance the TXC102 is etsi compliant with the addition of an external 3-pole pi filter. the filter gives the necessary rejection for second and third harmonics while introducing <1db of insertion loss at the desired transmit frequency. figures 9.1-9.3 show the schematic and recommended pcb layout, respectively, for an etsi compliant board. filter component values are given in table 9.1. the values for the matching circuit are given in table 2, page 6. table 9.1 band c16=c17 l4 433 6.8pf 18nh 868 3.3pf 12nh figure 9.1 www.rfm.com email: info@rfm.com page 28 of 30 ?by rf monolithics, inc. TXC102 - 4/8/08 figure 9.2 figure 9.3 pi filter www.rfm.com email: info@rfm.com page 29 of 30 ?by rf monolithics, inc. TXC102 - 4/8/08 ipc/jedec j-std-020c reflow profile www.rfm.com email: info@rfm.com page 30 of 30 ?by rf monolithics, inc. TXC102 - 4/8/08 10.0 package dimensions ? 6.4x5mm 16-pin tssop package (all values in mm) a c b f g e d l l1 r r1 0.20 gauge plane detail 1 2 3 0.25 detail dimensions in mm dimensions in inches symbol min nom max min nom max a 4.30 4.40 4.50 0.169 0.173 0.177 b 4.90 5.00 5.10 0.193 0.197 0.201 c 6.40 bsc. 0.252 bsc. d 0.19 0.30 0.007 0.012 e 0.65 bsc. 0.026 bsc. f 0.80 0.90 1.05 0.031 0.035 0.041 g 1.20 0.47 l 0.50 0.60 0.75 0.020 0.024 0.030 l1 1.00 ref. 0.39 ref r 0.09 0.004 r1 0.09 0.004 1 0 8 0 8 2 12 ref. 12 ref. 3 12 ref. 12 ref. |
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